The present invention relates to an ECL (Emitter Coupled Logic) circuit, more specifically to an ECL circuit in which power consumption per gate is small but the propagation delay time does not become large when it is used for driving a large capacitive load or a large fan-out circuit.
It is known that in an ECL circuit, each of the transistors in the circuit operates in a non-saturation mode, so a small signal operation of the logic circuit is possible. This enables a quicker operation as compared to other logic circuits. Therefore, the ECL circuits are used very widely for logic circuits which require a high speed operation. These circuits are sometimes called CML (Current Mode Logic) circuits. However, as the integration of the elements in LSIs (large scale integrated circuits) increases, the power consumption of the circuit becomes large and it is very important to decrease the heat generation in the LSI chips. Thus, it is desirable to make the circuit operate with as small a current as possible.
When a circuit is made to operate with a small current, its ability to drive a large capacitive load or a large fan-out circuit is decreased. Moreover, the operation speed decreases or the propagation delay time of the signal increases because of the parasitic capacitance of the load or the fan-out circuits. This is another difficulty which must be overcome in the LSI circuit design.